Field Of The Invention
The present disclosure relates to vertical channel field-effect transistors (FET), and in one aspect of the disclosure to printed vertical channel field-effect transistors on which vertical channel is produced by transferring one conducting layer over another conducting layer by using printed insulating adhesive layers.
Brief Description of the Related Art
Printed field-effect transistors (FET) are generating an immense amount of research interest in present times due to potential applications in the field of inexpensive electronics, and more specifically, use-and-throw disposable electronics. A transistor is a fundamental building block of electronic technologies. So far the transistors mostly use inorganic materials like silicon, germanium or III-V materials. Silicon-based transistors are produced in a clean room environment by using sophisticated and expensive machines. Printed transistors can be produced by using conventional printing methods which are available all over the world in printing presses. If an efficient transistor can be produced by the conventional printing method, then the transistor can make a non-skilled printer capable of producing/manufacturing electronics by using conventional printing machines in ambient conditions. In the context of this document, an “efficient” transistor means a transistor with a switch-on voltage of less than 5 Volt, a high on-off ratio, and a charge mobility higher than 0.1 cm/(V.s)
Printed electronics have immense potential in the realm of cheap, disposable and flexible electronics with easier manufacturability. The relative ease in processing of organic semi-conductive and conductive inks also adds to the attraction of developing printed electronic devices. Printed FETs form the backbone of the flexible, low cost circuitry required to control printed electronic devices. In order to bring low-cost, disposable printed electronics into the market, it is desirable to develop a process of fabricating printed FETs that does away with issues relating to expensive or complex production steps. Many efforts have been made to date to fabricate printed FETs that try to eliminate issues pertaining to low mobility of the charge carriers within the semiconducting material and thereby high operating voltages. Most methods include the usage of high mobility semiconductors, improved capacitance of the dielectric layer, reduction of contact resistance in the case of source, drain and gate contacts and minimizing dielectric and semiconducting active layer interface traps. Novel materials e.g. carbon nanotubes, graphene, semiconducting polymers (e.g. poly(3-hexylthiophene-2,5-diyl)), hybrid semiconductors (e.g. semiconducting conjugated polymers with inorganic nanoparticles), semiconducting perovskite etc. for printed FETs have demonstrated improvements in the device performance of the printed FETs, but current printed FETs still remain unsuitable for practical applications due to issues related to difficulty in fabrication processes, material handling and low charge carrier mobility. The reason behind this unsuitability is that the channel length produced by printing methods is still more than 10 micrometers.
The preferred architecture of the printed FET is that of coplanar interdigitated finger structures, as shown in FIG. 1A and FIG. 1B. FIG. 1A is the top view of the printed top gate FET 100 and FIG. 1B is the cross sectional view along the line A-A′. In the structure shown in FIG. 1A and 1B, the printed FET 100 comprises a first conducting layer 120 and a second conducting layer 130, printed in an interdigitated manner on a substrate 110. The first conducting layer 120 and the second conducting layer 130 represent a source-drain combination. The gap between the first conducting layer 120 and the second conducting layer 130 is the channel length. Over the first conducting layer 120 and the second conducting layer 130 a semiconducting layer 140 and a dielectric layer 150 are printed. A gate conducting layer 160 is printed as the final layer on top of the dielectric layer 150. Such architecture of the known printed FET has a large/long channel length (>20 micrometers). This compares to the channel length in a conventionally manufacture and commercially available FET in which the channel length is in the nanometer range.
The channel length of the printed FET is limited by the resolution of printing methods. Printing methods—offset, screen, gravure, flexo, ink-jet etc.—can not produce channel length of less than 20 micrometers, whilst still maintaining a high production yield. Producing source-drain interdigitated structure of a channel length less than 20 micrometers, by a printing method, creates a lot of short-circuits between source and drain, which hence lowers the production yield. Bottom gate FET produced by a printing method also encounters the same problem.
The vertical channel FET is an alternative to reducing the channel length substantially. Currently, the vertical channel FETs are produced by a combination of sophisticated techniques e.g. laser ablation, photoresist-masking, vacuum deposition. One technique of fabricating vertical channel FET has been reported in “Vertical Channel ZnO Thin-Film Transistors Using an Atomic Layer Deposition Method” by Chi-Sun Hwang et al, IEEE electron device letters, Vol. 35, no. 3, March 2014, pages 360-362. The vertical channel FET 200 is shown in FIG. 2. This describes a technique in which the architecture inculcates the process of depositing the first conducting layer 220 over a substrate 210 by radio frequency sputtering. An insulating layer 270 is patterned over the first conducting layer 220 using atomic layer deposition. A second conducting layer 230 is deposited over the insulating layer 270 using radio frequency sputtering. The resulting bilayer structure is then patterned using photolithography and wet etching processes to expose the source and drain regions. A semiconducting layer 240, a dielectric layer 250, and a gate conducting layer 260 are deposited respectively, using atomic layer deposition to complete the device. There are many reports related to vertical channel FET.
For example, European Patent number EP2059957-B1 describes an organic thin film transistor and a method for its fabrication, wherein a vertical channel architecture is incorporated. U.S. Pat. No. 6,664,576B1 describes a method of fabricating a vertical channel polymer based transistor. In the state-of-the-art vertical channel FETs, it is not possible to produce all the layers by printing alone, especially, it is not possible to produce a source-drain vertical channel. The problems associated with the production of vertical channel source-drain structure, by a printing method, are explained below in FIG. 3 and FIG. 4.
In the last decade, different functional inks have been developed for the printed FETs. These inks include: silver, PEDOT: PSS (Poly(2,3 -dihydrothieno-1,4-dioxin)-poly(styrenesulfonate)), semiconducting polymers, dielectrics etc. The printing method has not to date solved the issue of the limited size of the channel lengths. It is clear from FIG. 1A and FIG. 1B that decreasing channel length below 20 micrometers is not possible by a conventional printing method. In order to achieve this goal, it is required to develop a completely new printing method or make substantial modifications in the conventional printing machine. In either case, production of the printed FETs in mass scale by printers will not be possible since a printer will not like to buy a new printing machine. Therefore, there is a need to develop a FET structure with shorter channel length that can be produced by conventional printing machines in ambient conditions.
It is a common knowledge that conventional printing methods cannot print high resolution images in horizontal direction but the conventional printing methods can print very thin layers (even in nanometer range) in the vertical direction. Therefore, production of the vertical channel FETs by a conventional printing method, with the channel length in nanometer range, should be possible. The manufacture of the vertical channel, i.e. vertical source-drain structure by a conventional printing method, has another problem. This problem is explained in FIG. 3 and FIG. 4. In FIG. 3 (and FIG. 4) a first conducting layer 320 (420) is printed on a substrate 310 (410). On top of the first conducting layer 320 (420) is printed an insulating layer 370 (470). On top of the insulating layer 370 (470) is printed a second conducting layer 330 (430). As conventional printing methods are not good enough to print precisely in micrometer range, it is likely that the perimeter of the insulating layer 370 (470) and the perimeter of the second conducting layer 330 (430) will not overlap precisely. One possible outcome is that the edge of the insulating layer 370 and the edge of the second conducting layer 320 are separated by a gap of 302, which has a size in the order of several tens of micrometers (>20 micrometer), as shown in FIG. 3. Another possible outcome is that a portion 402 of the second conducting layer 430 can be printed over the first conducting layer 410 and will create a short circuit to the first conducting layer 420 bypassing the insulating layer 470, as shown on the right hand side in FIG. 4. Therefore, printing source-drain layers one over another, separated by an insulating layer, is not an option at all.
Therefore, there is a need to develop a vertical channel FET structure along with a method of its production, by using conventional printing methods. The vertical channel FET disclosed here comprises of a vertical channel source-drain structure that is produced by transferring one conducting layer over another conducting layer, by using an insulating adhesive layer. Transfer printing of a metallic layer to a non-conducting material (paper or plastic) is known in the printing industry and is called ‘hot foil transfer printing’ and ‘cold foil transfer printing’. Hot foil and cold foil transfer printings are used mostly for aesthetic purpose in packages, book, cards etc.